1. Field of the Invention
The present invention relates to floating point data calculation methods, and more specifically to a floating point calculation method and unit capable of efficiently performing a process of calculating floating point data to obtain integer data in floating point notation (the process is hereinafter referred to as integer representation) by rounding up or rounding down fractions below decimal point of floating point data and a semiconductor integrated circuit device provided with the same.
2. Description of the Background Art
As a numerical value must be represented as digital data having a prescribed number of bits in a calculator, real number data is generally represented as floating point data.
For the floating point data, a format having 32-bit length is generally employed in accordance with the IEEE standard.
FIG. 29 is a schematic diagram showing a structure of single-precision floating point data in accordance with the IEEE standard.
Referring to FIG. 29, the single-precision floating point data in accordance with the IEEE standard includes a sign bit of 1 bit, an exponent portion of 8 bits and a significand portion of 23 bits. A real number Z represented as floating point data is generally shown by the following equation (1).
Z=(xe2x88x921)Sxc3x97(1+F)xc3x972(e-b)xe2x80x83xe2x80x83(1)
In the above equation (1), F represents fractions below decimal point represented by the significand portion of 23 bits. S corresponds to data of the sign bit, and e corresponds to a decimal number representation of the exponent portion of 8 bits. A bias value in the case of an exponent is represented by b, for which a predetermined value is used in accordance with the standard. For example, b=127 in the single-precision floating point data, and b=1023 in double-precision floating point data.
In other words, if the bits of the significand portion are sequentially numbered as s1, s2, s3, . . . , starting from the first bit, the above equation (1) is expanded as the following equation (2).
(xe2x88x921)sxc3x97(1+(s1xc3x972xe2x88x921)+(s2xc3x972xe2x88x922)+(s3xc3x972xe2x88x923)+. . . )xc3x972(e-b)xe2x80x83xe2x80x83(2)
Thus, real number data in a wide range can be represented with high precision by a combination of the exponent and significand portions using the floating point data.
When calculation for image processing or the like is to be performed in the calculator, in some cases, a process of representing given real number data as an integer by rounding down or rounding up data corresponding to fractions below decimal point must frequently be performed at high speed.
As the floating point data is used to represent a real number value in a wide range by a combination of the exponent and significand portions, the number of digits of the data corresponding to the fractions below decimal point of the real number data differs from combination of the exponent and significand portions. Therefore, some special method must be used to efficiently perform integer representation of the floating point data.
An object of the present invention is to provide a floating point calculation method and unit capable of efficiently performing integer representation of floating point data by rounding down or rounding up fractions below decimal point and to provide a structure of a semiconductor integrated circuit device provided with the same.
In short, the present invention relates to a floating point calculation method performing integer representation of floating point data of a binary number including an exponent portion of M bits A: a natural number) and a significand portion of N bits (N: a natural number). The floating point calculation method includes steps of: outputting a calculation result X (X: an integer) obtained by subtracting a prescribed bias value from a decimal number value corresponding to the exponent portion of input data; and setting each bit of output integer data obtained by representing the input data as an integer in accordance with a combination of calculation result X, a sign of the input data and an integer representation designation signal designating by which one of rounding up and rounding down the integer representation is to be performed.
According to another aspect of the present invention, the present invention relates to a floating point calculation unit performing integer representation of floating point data of a binary number having a sign bit, an exponent portion of M bits (M: natural number) and a significand portion of N bits (N: natural number). The floating point calculation unit includes an input circuit, an exponent portion calculating circuit, an integer-represented data setting circuit and an output circuit.
The input circuit receives input data. The exponent portion calculating circuit outputs a calculation result X (X: integer) obtained by subtracting a prescribed bias value from a decimal number value corresponding to the exponent portion of the input data. The integer-represented data setting circuit receives the input data and sets each bit of output integer data in accordance with a combination of calculation result X, a sign of the input data and the integer representation designation signal designating by which one of rounding up and rounding down the integer representation is to be performed. The output circuit outputs the output integer data.
According to still another aspect, the present invention relates to a semiconductor integrated circuit device performing a prescribed data process in accordance with an externally applied designation signal. The semiconductor integrated circuit device includes an input/output circuit, a control circuit, a memory circuit, a system bus and a dedicated calculating circuit.
The input/output circuit externally transmits/receives a signal. The control circuit generates an internal control signal to perform a process corresponding to an instruction signal. The memory circuit stores data. The system bus transmits the designation signal and data to each circuit in the semiconductor integrated circuit device. The dedicated calculating circuit has a function of performing integer representation of floating point data of the binary number.
The dedicated calculating circuit includes: a logic circuit controlling an operation of the dedicated calculating circuit in accordance with the internal control signal: a sub memory circuit storing data in accordance with an instruction of the logic circuit; and a floating point calculating circuit performing integer representation of the floating point data in accordance with the instruction of the logic circuit. The floating point data includes a sign bit, an exponent portion of M bits (M: a natural number) and a significand portion of N bits (N: a natural number). The floating point calculating circuit includes: an input circuit receiving input data; an exponent portion calculating circuit outputting a calculation result X (X: an integer) obtained by subtracting a prescribed bias value from a decimal number value corresponding to the exponent portion of the input data; an integer-represented data setting circuit setting each bit of the output integer data in accordance with a combination of calculation result X, a sign of the input data and an integer representation designation signal designating by which one of rounding up and rounding down the integer representation is to be performed; and an output circuit outputting the output integer data.
Thus, a main advantage of the present invention is that the integer representation can be performed at high speed as integer representation of the floating point data by rounding up or rounding down is performed without a step of converting the format of the floating point data to that of fixed point data.
In addition, as the calculation unit performing integer representation of the floating point data is obtained only by a circuit which processes data having the same number of bits as that of the input circuit without data format conversion, integer representation of the floating point data can be performed at high speed by a small circuitry which is advantageous in terms of a layout.
Further, the floating point calculation unit is provided which is capable of performing integer representation of the floating point data only by a circuit which processes data having the same number of bits as that of the input data without data format conversion. Therefore, the semiconductor integrated circuit device is capable of efficiently and frequently performing the integer representation of the data at high speed.